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digital mems vibration sensor w/ embedded rf transceiver preliminary technical data adis16000/adis16229 rev. pra information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2013 analog devices, inc. all rights reserved. features wireless vibration system, 862mhz C 928mhz clear channel assessment/packet collision avoidance error detection and correction in rf protocol programmable rf output power gateway node (adis16000) spi to rf function manage up to 6 sensor nodes sensor node (adis16229) dual-axis, 18g mems accelerometer 5.5khz resonant frequency digital range settings: 0 g to 1 g /5 g /10 g /20 g sample rate up to 20ksps programmable wake-up capture, update cycle times fft, 512-point, real valued rectangular, hanning, flat top window options programmable decimation filter, 11 rate settings multi-record capture for selected filter settings manual capture mode for time domain data collection programmable fft averaging: up to 255 averages record storage: 14 fft records on all three axes (x, y) programmable alarms, 6 spectral bands, 2 levels adjustable response delay to reduce false alarms internal self-test with status flags digital temperature and power supply measurements identification registers: serial number, device id, user id 47mm x 38mm pcb package with sma antenna interface single-supply operation: 3.0 v to 3.6 v operating temperature range: ?40c to +85c applications vibration analysis condition monitoring machine health instrumentation, diagnostics safety shutoff sensing general description the adis16000 and adis16229 enable creation of a simple wireless vibration-sensing network for a wide variety of industrial-equipment applications. . the adis16000 provides the gateway function, which manages the network, while the adis16229 provides the remote sensing function. the adis16229 isesnor is a complete wireless vibration sensor node that combines dual-axis acceleration sensing with advanced time domain and frequency domain signal processing. time domain signal processing includes a programmable decimation filter and selectable windowing function. frequency domain processing includes a 512-point, real-valued fft, fft magnitude averaging, and programmable spectral alarms. the fft record storage system offers users the ability to track changes over time and capture ffts with multiple decimation filter settings. the adis16229s dynamic range, bandwidth, sample rate and noise performance are well suited for a wide variety of machine health and production equipment monitoring systems. this devices also provides a number of wireless configuration parameters enable a wide level of flexibility in managing the trade-off between battery life and communication frequency. the adis16000 spi interface provides simple connectivity with most embedded processor platforms and the sma connector interface enables the use of many different antennas. this module supports up to six adis16229 devices at one time, using a proprietary wireless protocol. both adis16000 and adis16229 modules are in in 47.0x37.6x22.6mm pcb structures, have an sma connector for simple antenna connection, have two mounting holes for simple installation and support operation over a temperature range of - 40c to +85c. the adis16000 also includes a standard 1mm, 14-pin connector for connecting to an embedded processor system. the adis16229 provides a lead structure that enables simple connection with standard batteries. functional block diagram figure 1.
adis16000/adis16229 preliminary technical data rev. pra | page 2 of 37 table of contents features .............................................................................................. 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
preliminary technical data adis16000/adis16229 rev. pra | page 3 of 37 specifications t a = ?40c to +125c, vdd = 3.3 v, unless otherwise noted. table 1. parameter test conditions/comments min typ max unit accelerometers (adis16229) measurement range 1 t a = 25c 18 g sensitivity, fft t a = 25c, 0 g to 20 g range setting 0.3052 m g /lsb sensitivity, time domain t a = 25c 0.6104 m g /lsb sensitivity error t a = 25c 0.3 6 % nonlinearity with respect to full scale 0.2 1.25 % cross-axis sensitivity 4 % alignment error with respect to package mounting holes 2.3 degrees offset error t a = 25c 0.01 1 g offset temperature coefficient 2 m g /c output noise t a = 25c, 20.48 khz sample rate, time domain 11 m g rms output noise density t a = 25c, 10 hz to 1 khz 0.248 m g /hz bandwidth 5% flatness, 2 , see figure 19 840 hz sensor resonant frequency 5.5 khz logic inputs 3 (adis16000) input high voltage, v inh 0.7 x vdd v input low voltage, v inl 0.2xvdd v input leakage current all except rst tbd a rst ?1 ma input capacitance, c in 10 pf digital outputs 3 output high voltage, v oh i source = 1 ma vdd-0.4 v output low voltage, v ol i sink = 1 ma 0.36 v flash memory endurance 4 20,000 cycles data retention 5 t j = 85c, see figure 23 20 years start-up time 6 initial startup adis16000 200 ms adis16229 100 ms reset recovery 7 adis16000 200 ms adis16229 50 ms sleep mode recovery adis16229 2.3 ms conversion rate rec_ctrl1[11:8] = 0x1 (sr0 sample rate selection) 20 ksps clock accuracy 3 % power supply operating voltage range, vdd 3.0 3.3 3.6 v power supply current, adis16229 transmission mode, 10dbm, +25c 39 41 ma transmission mode, 10dbm, -40c to +85c tbd transmission mode, -1dbm, +25c 18 tbd ma transmission mode, -1dbm, -40c to +85c tbd receive mode, +25c 20 tbd ma receive mode, +40c to +85c tbd data capture mode, no transceiver activity, +25c 7.2 sleep mode, t a = 25c 2.5 a power supply current, adis16000 transmission mode, 10dbm, +25c 37 ma transmission mode, -1dbm, +25c 18 ma receive mode, +25c 20 ma
adis16000/adis16229 preliminary technical data rev. pra | page 4 of 37 1 the maximum range depends on the frequency of vibration. 2 assumes that frequency flatness calibration is enabled. 3 the digital i/o signals are 5 v tolerant. 4 endurance is qualified as per jedec standard 22, method a117 and measured at ?40c, +25c, +85c, and +125c. 5 retention lifetime equivalent at junction temperature (t j ) = 85c as per jedec standard 22, method a117. retention lifetime de pends on junction temperature. 6 the start-up times presented reflect the time it takes for data collection to begin. 7 applies to the reset line ( rst = 0) and the software reset command (glob_cmd[7] = 1). the rst pin must be held low for at least 10 s.
preliminary technical data adis16000/adis16229 rev. pra | page 5 of 37 timing specifications t a = 25c, vdd = 3.3 v, unless otherwise noted. table 2. parameter description min 1 typ max unit f sclk sclk frequency 0.01 2.5 mhz t stall stall period between data, between 16 th and 17 th sclk 25 s t cs chip select to sclk edge 48.8 ns t dav dout valid after sclk edge 100 ns t dsu din setup time before sclk rising edge 24.4 ns t dhd din hold time after sclk rising edge 48.8 ns t sr sclk rise time 12.5 ns t sf sclk fall time 12.5 ns t df , t dr dout rise/fall times 5 12.5 ns t sfs cs high after sclk edge 5 ns 1 guaranteed by design, not tested. timing diagrams cs sclk dout din 1 2 3 4 5 6 15 16 r/w a5 a6 a4 a3 a2 d2 msb db14 d1 lsb db13 db12 db10 db11 db2 lsb db1 t cs t sfs t dav t sr t sf t dhd t dsu 10069-002 figure 2. spi timing and sequence cs sclk t stall 10069-003 figure 3. din bit sequence
adis16000/adis16229 preliminary technical data rev. pra | page 6 of 37 absolute maximum ratings table parameter rating acceleration any axis, unpowered 2000 g any axis, powered 2000 g vdd to gnd ?0.3 v to +3.96 v digital input voltage to gnd ?0.3 v to +3.96 v digital output voltage to gnd ?0.3 v to +3.96 v temperature operating temperature range ?40c to +85c storage temperature range ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 4. package characteristics package type ja jc device weight 15-lead module 31c/w 11c/w 6.5 grams esd caution
preliminary technical data adis16000/adis16229 rev. pra | page 7 of 37 pin configuration and fu nction descriptions figure 4. adis16000 pin assignments figure 5. pin configuration table 5. pin function descriptions pin no. mnemonic type 1 description 1, 2 vdd s power supply, 3.3 v. 3, 4 gnd s ground. 5 do2 i/o digital input/output line 2. 6, 8, 9 , 10 dnc i/o do not connect 7 dout o spi, data output. dout is an output when cs is low. when cs is high, dout is in a three- state, high impedance mode. 9 sclk i spi, serial clock. 11 cs i spi, chip select. 12 din/rxd i spi, data input. 13 do1 i/o digital input/output line 1. 14 rst i reset, active low. 1 s is supply, o is output, i is input, and i/o is input/output.
adis16000/adis16229 preliminary technical data rev. pra | page 8 of 37 theory of operation the adis16000 is the gateway node and the adis16229 serves as the remote sensor node in a wireless vibration monitoring system. using a proprietary wireless protocol, one adis16000 can support up to six adis16229 nodes at one time in local star network configuration (see figure 8). as the gateway node, the adis16000s spi interface provides access to an addressable register map that manages configuration parameters (gateway and sensor node), remote alarm flags and remote vibration data. the adis16000s spi interface enables simple connection to most embedded processors and its standard sma connector supports direct connection to a wide variety of antennas. the adis16229 only requires an antenna and battery to start-up, connect with the adis16000 and begin operation. sensing element digital vibration sensing in the adis16229 starts with a mems accelerometer core on two different axes. accelerometers translate linear changes in velocity into a representative electrical signal, using a micromechanical system like the one shown in figure 6. the mechanical part of this system includes two different frames (one fixed, one moving) that have a series of plates to form a variable, differential capacitive network. when experiencing the force associated with gravity or acceleration, the moving frame changes its physical position with respect to the fixed frame, which results in a change in capacitance. tiny springs tether the moving frame to the fixed frame and govern the relationship between acceleration and physical displacement. a modulation signal on the moving plate feeds through each capacitive path into the fixed frame plates and into a demodulation circuit, which produces the electrical signal that is proportional to the acceleration acting on the device. movable frame acceler a tion unit forcing cell unit sensing cell moving plate fixed plates plate capacitors anchor anchor 10069-005 figure 6. mems sensor diagram signal processing figure 9 offers a simplified block diagram for the adis16229 . the signal processing stage includes time-domain data capture, digital decimation/filtering, windowing, fft analysis, fft averaging, and record storage. see figure 16 for more details on the signal processing operation. sensor communication the adis16000 provides access to the adis16229 through dedicated pages in the register structure. when the adis16000 communicates with a remote adis16229, it copies all configuration information in these registers to their respective locations in the adis16229 and acquires all of the data in the adis16229s output registers/data records. gateway communication spi interface the data collection and configuration command uses the spi, which consists of four wires. the chip select ( cs ) signal activates the spi interface, and the serial clock (sclk) synchronizes the serial data lines. input commands clock into the din pin, one bit at a time, on the sclk rising edge. output data clocks out of the dout pin on the sclk falling edge. since the adis16000 serves only as a spi slave, the dout contents reflect the information requested using a din command. register organization the adis16000s memory map contains 7 pages of user accessible registers, which enable simple organization of both local (gateway) and remote (sensor) functions. each page has a page control register (page_id) address 0x00. before accessing a register within a particular page, write that pages identification number to this register. for example, write 2 to the page_id register to access sensor node #2. once a particular page has been accessed, there is no need to write the same value to page_id, in order to access the rest of the registers within that page each 16-bit register has its own unique bit assignment and two addresses: one for its upper byte and one for its lower byte. table 9 and table 10 provide more details on these memory maps, which list each register, along with its function and lower byte address. table 6. adis16000 register map page organization page_id function reference 0x0000 gateway configuration table 9 0x0001 sensor node #1 table 10 0x0002 sensor node #2 table 10 0x0003 sensor node #3 table 10 0x0004 sensor node #4 table 10 0x0005 sensor node #5 table 10 0x0006 sensor node #6 table 10 dual-memory structure the user registers provide addressing for all input/output operations in the spi interface. the control registers use a dual-
preliminary technical data adis16000/adis16229 rev. pra | page 9 of 37 memory structure. the controller uses sram registers for normal operation, including user-configuration commands. the flash memory provides nonvolatile storage for control registers that have flash backup (see table 9 and table 10). when the device powers on or resets, the flash memory contents load into the sram, and the device starts producing data according to the configuration in the control registers. storing configuration data in the flash memory requires a manual flash update command. for the adis16000, set din = 0x8000 (access page 0), then set din = 0x9240 (set glob_cmd[6] = 1). for a remote adis16229, using the following steps to update its flash: (1) turn to its page (din = 0x8001, to access note, for example), (2) set din = 0xb640 (glob_cmd[6] = 1), (3) set din = 0x8000 (turn to page 0) and (4) set din = 0x9202 (glob_cmd[8] = 1). nonvolatile flash memory (no spi access) manual flash backup start-up reset volatile sram spi access 10069-007 figure 7. sram and flash memory diagram figure 8. star wireless network example figure 9. adis16229 simplified block diagram
adis16000/adis16229 preliminary technical data rev. pra | page 10 of 37 adis16000 basic operation once it has appropriate power on the vdd pin, the adis16000 will automatically begin a self-initialization process. once this process is complete, the spi interface activates and provides access to its register structure. the spi interface supports connectivity with most embedded processor platforms, using the connection diagram in figure 10. the factory default configuration for do1 provides a busy indicator signal that indicates when to avoid spi communication requests. figure 10. electrica l hook-up diagram table 7. generic master processor pin names and functions pin name function ss slave select sclk serial clock mosi master output, slave input miso master input, slave output irq1, irq2 interrupt request inputs (optional) the adis16000 spi interface supports full duplex serial communication (simultaneous transmit and receive) and uses the bit sequence shown in figure 14. table 8 provides a list of the most common settings that require attention to initialize a processor serial port for the adis16000 spi interface. table 8. generic master processor spi settings processor setting description master the adis16000 operates as a slave. sclk rate 2.5 mhz bit rate setting. spi mode 3 clock polarity/phase (cpol = 1, cpha = 1). msb first bit sequence. 16-bit shift register/data length. table 9 and table 10 provide lists of user registers with their lower byte addresses. each register consists of two bytes that each has its own unique 7-bit address. figure 11 relates the bits of each register to their upper and lower addresses. upper byte 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lower byte 10069-009 figure 11. generic register bit definitions spi write commands user control registers govern many internal operations. the din bit sequence in figure 14 provides the ability to write to these registers, one byte at a time. some configuration changes and functions require only one write cycle. for example, set page_id[7:0] = 1 (din = 0x8001) to select page 1 of the register map. figure 12. spi sequence for selecting page 1 for access (din = 0x8001) spi read commands a single register read requires two 16-bit spi cycles that also use the bit assignments that are shown in figure 14. the first sequence sets r /w = 0 and communicates the target address (bits[a6:a0]). bits[d7:d0] are dont care bits for a read din sequence. dout clocks out the requested register contents during the second sequence. the second sequence can also use din to set up the next read. figure 13 provides a signal diagram for all four spi signals while reading the prod_id. in this diagram, din = 0x1600 and dout reflects the decimal equivalent of 16,000. figure 13. example spi read, prod_id (page 0), second sequence r/w r/w a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 notes 1. dout bits are based on the previous 16-bit sequence (r/w = 0). cs sclk din dout a6 a5 db13 db14 db15 10069-012 figure 14. example spi read sequence
preliminary technical data adis16000/adis16229 rev. pra | page 11 of 37 table 9. user register memory map, page_id = 0x0000 register name access flash backup address default function reference page_id read/write n/a 0x00 0x0000 page identifier network_id read/write yes 0x02 1234 network identifier, unique to a network flash_cnt read yes 0x04 n/a flash update counter nw_error_stat read no 0x06 0x0000 network error indicators tx_pwr_ctrl_g read/write yes 0x08 0x0000 transmission power control, gateway rssi_g read no 0x0a 0x0000 received signal strength temp_out_g read no 0x0c 0x8000 output, temperature supply_out_g read no 0x0e 0x8000 output, supply voltage beacon_setup read/write yes 0x10 0x0000 beacon frequency glob_cmd read/write no 0x12 0x0000 system commands cmd_data read/write no 0x14 0x0000 data to sensor nodes prod_id read only yes 0x16 0x3e80 product identifier, 16000 reserved n/a no 0x18 n/a reserved reserved n/a no 0x1a n/a reserved reserved n/a no 0x1c n/a reserved reserved n/a no 0x1e n/a reserved reserved n/a no 0x20 n/a reserved reserved n/a no 0x22 n/a reserved lot_id1 read only no 0x24 n/a lot identifier 1 lot_id2 read only no 0x26 n/a lot identifier 2 reserved n/a no 0x28 n/a reserved gpo_ctrl read/write yes 0x2a n/a general-purpose output control
adis16000/adis16229 preliminary technical data rev. pra | page 12 of 37 table 10. user register memory map, page_id 0x0001 register name access flash backup address default 1 function reference page_id read/write n/a 0x00 n/a page identifier sens_id read only yes 0x02 n/a sensor identifier flash_cnt read only yes 0x04 n/a st atus, flash memory write count x_buf read only no 0x06 0x8000 output, buffer for x-axis acceleration data table 59 y_buf read only no 0x08 0x8000 output, buffer for y-axis acceleration data table 60 temp_out read only no 0x0a 0x8000 o utput, temperature during capture supply_out read only no 0x0c 0x8000 o utput, power supply during capture fft_avg1 read/write yes 0x0e 0x8000 control, fft average size of 1, sr0 and sr1 table 34 fft_avg2 read/write yes 0x10 0x0108 control, fft average size of 2, sr2 and sr3 table 35 buf_pntr read/write no 0x12 0x0101 control, buffer address pointer table 57 rec_pntr read/write no 0x14 0x0000 control, record address pointer table 58 x_sens read/write no 0x16 control, x-axis acceleration scale adjustment table 32 y_sens read/write no 0x18 control, y-axis acceleration scale adjustment table 33 rec_ctrl1 read/write yes 0x1a 0x0002 record control register table 27 rec_ctrl2 read/write yes 0x1c 0x000f record control register table 30 0x1e alm_f_low read/write yes 0x20 0x0000 spectral alarm band, low frequency table 43 alm_f_high read/write yes 0x22 0x0000 spectral alarm band, high frequency table 44 alm_x_mag1 read/write yes 0x24 0x0000 spectral al arm band, x-axis, alarm 1 magnitude table 45 alm_y_mag1 read/write yes 0x26 0x0000 spectral al arm band, y-axis, alarm 1 magnitude table 46 alm_x_mag2 read/write yes 0x28 0x0000 spectral al arm band, x-axis, alarm 2 magnitude table 47 alm_y_mag2 read/write yes 0x2a 0x0000 spectral al arm band, y-axis, alarm 2 magnitude table 48 alm_pntr read/write no 0x2c 0x0000 spectral alarm band pointer table 42 alm_s_mag read/write yes 0x2e 0x0000 alar m, system alarm threshold table 49 alm_ctrl read/write yes 0x30 0x0000 alarm, control register table 41 avg_cnt read/write yes 0x32 0x9630 sample rate control (average count) table 28 diag_stat read only no 0x34 0x0000 system status register glob_cmd write only no 0x36 0x0000 gl obal command register table 74 alm_x_stat read only no 0x38 0x0000 alarm, x-axis status register table 50 alm_y_stat read only no 0x3a 0x0000 alar m, y-axis status register table 51 alm_x_peak read only no 0x3c 0x0000 al arm, x-axis peak level table 52 alm_y_peak read only no 0x3e 0x0000 al arm, y-axis peak level table 53 time_stamp_l read only no 0x40 0x0000 time stamp, low integer table 72 time_stamp_h read only no 0x42 0x0000 time stamp, high integer table 73 alm_x_freq read only no 0x44 0x0000 alarm, x-axis, frequency of alm_x_peak table 54 alm_y_freq read only no 0x46 0x0000 alarm, y-axis, frequency of alm_y_peak table 55 prod_id read only yes 0x48 0x0000 product identification register rec_flsh_cnt read only no 0x4a 0x0000 table 39 rec_info1 read only no 0x4c 0x0000 record settings 1 table 70 rec_info2 read only no 0x4e 0x0000 record settings 2 table 71 rec_cntr read only no 0x50 0x0000 record counter table 37 pkt_time_l read only yes 0x52 0x0000 received packet time stamp, low integer pkt_time_h read only yes 0x54 0x0000 received packet time stamp, high integer pkt_err_stat read only yes 0x56 0x0000 missed packets/error indicator tx_pwr_ctrl_s read/write yes 0x58 0x0000 transmission power control rssi_s read only yes 0x5a 0x0000 received signal strength indicator rf_mode read/write yes 0x5c wireless communication configuration updat_int read/write yes 0x5e 0x0000 update interval int_scl read/write no 0x60 0x0000 update interval scale beacon_int read/write yes 0x62 0x0000 beacon interval user_scr read only yes 0x64 0x0000 user scratch register
preliminary technical data adis16000/adis16229 rev. pra | page 13 of 37 reserved n/a n/a 0x66 n/a reserved lot_id1 read only yes 0x68 n/a lot identification 1 lot_id2 read only yes 0x6a n/a lot identification 2 reserved n/a n/a 0x6c n/a reserved reserved n/a n/a 0x6e n/a reserved x_anull read only yes 0x70 0x0000 automatic null value, x-axis y_anull read only yes 0x72 0x0000 automatic null value, y-axis updt_flag read/write yes 0x74 register update tracking register 1 all registers in pages 1, 2, 3, 4, 5 and 6 will read 0x0000, prior to connecting with the adis16229 network management once they have an appropriate supply voltage across their vdd and gnd pins, both adis16000 and adis16229 will self-initialize and prepare themselves for connecting. after completing this process, the adis16229 will start sending connection requests to any available adis16000 devices that are within range. the system microcontroller manages the adis16000s response to these requests, using the cmd_data (see table 11) and glob_cmd registers (see table 12), which are both in page 0 of the adis16000. adding an adis16229 network requires two steps: (1) write the node number (between 0 and 6) to the cmd_data register and then (2) set glob_cmd[0] = 1 (din = 0x9201, in page 0). after this second step, the connection process can take up to 3 minutes after writing this code. removing a sensor from the network uses a similar two-step process: (1) write the sensor node number to the cmd_data register and then (2) set glob_cmd[8] = 1 (din = 0x9301, page 0). set glob_cmd[1] = 1 (din = 0x9202) to initial an update of all of the registers, except those associated with the spectral alarms. set glob_cmd[12] = 1 (din = 0x9310) to update all of the alarm registers, after configuring them. separating this function will help manage the flash memory endurance. table 11. cmd_data, page 0, low-byte address = 0x14, read/write bits description (default = 0x0000) [15:4] not used [3:0] sensor node for glob_cmd[1] and glob_cmd[0] commands. range = 000 (0) to 110 (6) table 12. glob_cmd page 0, low-byte address = 0x12, write only bits description execution time [15:8] not used 8 remove sensor node in cmd_data from the network 7 software reset 6 save registers to flash memory 5 flash test, compare sum of flash memory with factory value 4 clear diag_stat register 3 restore factory register settings, including capture buffer and alarm registers 2 self-test, result in diag_stat[5] 1 update sensor node in cmd_data register, in one of the manual modes 0 add sensor node in cmd_data to the network after connecting with an adis16229, the adis16000 will automatically copy the contents from its own network_id[7:0] location (see table 13) to the sens_id[7:0] location in the adis16229s page. (see table 14). table 13. network_id page 0, low-byte address = 0x02, read/write bits description (default = 0x1234) [15:0] network identification number the sens_id register will contain the value 0x0000 when not connected to a network. when connected to the network, as node 1, it will contain 0xad34. table 14. sens_id page 1-6, low-byte address = 0x02, read only bits description (default = 0xaaaa) [15:0] sensor identification receiver signal strength the rssi_g (see table 15) and rssi_s (see table 16) provide tools for tuning the transmission power control at each location. in order to maintain effective communication, keep the transmission power high enough to maintain at least -94dbm in these registers.
adis16000/adis16229 preliminary technical data rev. pra | page 14 of 37 table 15. rssi_g page 0, low byte address = 0x0a, read only bits description (default = 0x) [15:0] received signal strength twos complement format, 1 lsb = 1dbm 0x0000 = 0dbm 0xffa2 = -94dbm table 16. rssi_s page 1-6, low byte address = 0x5a, read only bits description (default = 0x1100) [15:0] received signal strength twos complement format, 1 lsb = 1dbm 0x0000 = 0dbm 0xffa2 = -94dbm transmission power control both adis16000 and adis16229 units provide controls for transmission power in a registers called, tx_pwr_ctrl_g (see table 17) and tx_pwr_ctrl_s. the registers provide users with the ability to optimize the transmission power for battery optimization and to manage interference influence on other networks. note that compliance with fcc part 15.249 involves limiting the transmission power to -1dbm. table 17. tx_pwr_ctrl_g page 0, low byte address = 0x08, read/write bits description (default = 0x) [15:5] not used (do not care) [40] transmission power, offset binary format 1lsb = 1.6dbm (25.5/15) 0 = -15.5dbm (minimum) f = +10dbm (maximum) table 18. tx_pwr_ctrl_s page 1-6, low byte address = 0x58, read/write bits description (default = 0x) [15:5] not used (do not care) [40] transmission power, offset binary format 1lsb = 1.6dbm (25.5/15) 0 = -15.5dbm (minimum) f = +10dbm (maximum) wireless configuration the rf_mode (see table 19) register provides a number of important wireless configuration parameters. note that when the transmission power exceeds -1dbm, fcc part 15.247 requires the use of frequency-hopping. table 19. rf_mode page 0, low byte address = 0x58, read/write bits description (default = 0x) [15:9] not used (do not care) [8] complete register dump during update cycle (0 = enable, 1 = disable) [7] periodic wake-up/beacon synchronization (0 = disable, 1 = enable) [6] frequency hoping (0 = disable, 1 = enable) [5] complete synchronization after missing 2 beacons (0 = disable, 1 = enable) [4:2] not used (do not care) [1] update gateway on alarm only (0 = disable, 1 = enable) [0] update gateway on beacon synchronization (0 = disable, 1 = enable) the updat_int (see table 20) and int_scl (see table 21) registers establish the time between wake-up events, where the remote adis16229 captures data, analyzes it and communicates the information. table 20. updat_int page 1-6, low byte address = 0x5e, read/write bits description (default = 0x) [15:0] offset binary number, scale factor set by int_scl register table 21. int_scl page 1-6, low byte address = 0x60, read/write bits description (default = 0x) [15:2] not used (do not care) [1:0] scale factor 00 = 30.52sec/lsb, maximum = 2 seconds 01 = 0.488msc/lsb, maximum = 31.98 seconds 10 = 1/128 sec/lsb, maximum = 512 seconds 11 = 1 sec/lsb, maximum = 18.2 hours the beacon synchronization function uses periodic monitoring for drift in sensor node clocks and limits their sleep time to 30 minutes (or less) in order to maintain consistent synchronization. the beacon_setup (see table 22) register provides a user control for this function. when operating in real-time mode (rec_ctrl1 register, see table 27) this mode is not necessary and automatically turns off. table 22. beacon_setup page 0, low byte address = 0x10, read/write bits description (default = 0x) [15:1] not used 0 1 = beacon synchronization enable
preliminary technical data adis16000/adis16229 rev. pra | page 15 of 37 0 = beacon synchronization disable the beacon_int (see table 23) register sets the interval time between re-synchronizing events with the adis16000 (gateway). table 23. beacon_int page 1-6, low byte address = 0x62, read/write bits description (default = 0x) [15:0] offset binary number, scale factor set by int_scl register communication tools the pkt_time_h (upper word) and pkt_time_l (lower word) registers provide a 32-bit timer for tracking the relative times associated with packet transmission times. this maximum value for this number is 49.71 days. at this point, the registers start over at 0x0000. table 24. pkt_time_h page 1-6, low byte address = 0x54, read/write bits description (default = n/a)) [15:0] offset binary number, upper word table 25. pkt_time_l page 1-6, low byte address = 0x52, read/write bits description (default = n/a) [15:0] offset binary number, lower word, 1 lsb = 1msec the nw_error_stat (see table 26) register provides all of the error flags associated with the wireless communication. table 26. nw_error_stat page 0, low byte address = 0x06), read/write bits description (default = 0x1100) [15:12] sensor node associated present error flags in this register [11:10] not used 9 received packet from an unknown device. 8 packet synchronization failure, from the most recent received packet 7 no response from one or more sensor nodes during beacon synchronization 6 failed to receive a packet from the sensor node 5 packet length mismatch 4 missing packet 3 packets received out of sync 2 failure to receive acknowledgement from a sensor node 1 low signal strength from a sensor node, read rssi_s register for power level of this signal. see table 16 0 crc mismatch error associated with the most recent packet from the sensor node packet
adis16000/adis16229 preliminary technical data rev. pra | page 16 of 37 sensor node recording mode/signal processing the adis16229 provides a complete sensing system for recording and monitoring vibration data. figure 15 provides a simplified block diagram for the signal processing associated with spectral record acquisition on both axes (x and y). user registers provide controls for data type (time or frequency), trigger mode (manual or automatic), collection mode (real time or capture), sample rates/filtering, windowing, fft averaging, spectral alarms, and i/o management. recording mode the recording mode selection establishes the data type (time or frequency domain), trigger type (manual or automatic), and data collection (captured or real time). the rec_ctrl1[1:0] bits (see table 27) provide four operating modes: manual fft, automatic fft, manual time capture, and real time. after setting rec_ctrl1, the manual fft, automatic fft, and manual time capture modes require a start command to start acquiring a spectral or time domain record. all of these modes automatically trigger when the sensor receives the configuration packet from the gateway. set glob_cmd[11] = 1 to halt the operation and wait for further instructions from the adis16000.. table 27. rec_ctrl1 page 1-6, low byte address = 0x1a, read/write bits description (default = 0x1100) [15:14] not used (dont care). [13:12] window setting. 00 = rectangular, 01 = hanning, 10 = flat top, 11 = n/a. 11 sr3, 1 = enabled for fft, 0 = disable. sample rate = 20,000 2 avg_cnt[15:12] (see table 28). 10 sr2, 1 = enabled for fft, 0 = disable. sample rate = 20,000 2 avg_cnt[11:8] (see table 28). 9 sr1, 1 = enabled for fft, 0 = disable. sample rate = 20,000 2 avg_cnt[7:4] (see table 28). 8 sr0, 1 = enabled for fft, 0 = disable. sample rate = 20,000 2 avg_cnt[3:0] (see table 28). 7 power-down between each recording. 1 = enabled. [6:4] not used (dont care). [3:2] storage method. 00 = none, 01 = alarm trigger, 10 = all, 11 = n/a. [1:0] recording mode. 00 = manual fft, 01 = automatic fft, 10 = manual time capture, 11 = real-time sampling/data access. manual fft mode set rec_ctrl1[1:0] = 00 to place the device in manual fft mode, which will result in triggering a single fft cycle. when the spectral record is complete, the device will transmit the data to the adis16000 and wait for another start command. automatic fft mode set rec_ctrl1[1:0] = 01 to place the device in automatic fft mode. use the updat_int and int_scl registers to establish the period between wake-up times, which triggers data capture, fft computation and analysis. manual time capture mode set rec_ctrl1[1:0] = 10 to place the device into manual time capture mode, which will result in triggering a single time domain data capture. when the device is operating in this mode, 512 samples of time domain data are loaded into the buffer for each axis. this data goes through all time domain signal processing, except the pre-fft windowing, prior to loading into the data buffer for user access. when the data record is complete, the device will transmit the data to the adis16000 and wait for another start command. 10069-023 mems adc processing data buffer records spi and registers figure 15. simplified block diagram
preliminary technical data adis16000/adis16229 rev. pra | page 17 of 37 real-time mode set rec_ctrl1[1:0] = 11 to place the device into real-time mode. in this mode, the device samples only one axis, at a rate of 5 ksps, and provides data on its output register at the sr0 sample rate setting in avg_cnt[3:0] (see table 28). select the axis of measurement in this mode by reading its assigned register. for example, select the x-axis by reading x_buf, using din = 0x1400. see table 59 or table 60 for more information on the x_buf registers. no other adis16229 nodes will be able to communicate with the adis16000 when one of them is in real- time mode. spectral record production the adis16229 produces a spectral record by taking a time record of data on both axes, then scaling, windowing, and performing an fft process on each time record. this process repeats for a programmable number of fft averages, with the fft result of each cycle accumulating in the data buffer. after com- pleting the selected number of cycles, the fft averaging process completes by scaling the data buffer contents. then the data buffer contents are available to the spi and output data registers. sample rate/filtering the sample rate for each axis is 20 ksps. the internal adc samples both axes in a time-interleaving pattern (x1, y1, x2, y2) that provides even distribution of data across the data record. the averaging/decimating filter provides a control for the final sample rate in the time record. by averaging and decimating the time domain data, this filter provides the ability to focus the spectral record on lower bandwidths, which produces finer frequency resolution in each fft frequency bin. avg_cnt (see table 28) provides the setting for the four different sample rate options in rec_ctrl1[11:8] (srx, see table 27). all four options are available when using the manual fft, automatic fft, and manual time capture modes. when more than one sample rate option is enabled while the device is in one of the manual modes, the device produces a spectral record for one srx at a time, starting with the lowest number. after completing the spectral record for one srx option, the device waits for another start command before producing a spectral record for the next srx option that is enabled in rec_ctrl1[11:8]. when more than one sample rate option is enabled while the device is in the automatic fft mode, the device produces a spectral record for one srx option, and then waits for the next automatic trigger, which occurs based on the updat_int and int_scl registers. see figure 17 for more details on how multiple srx options influence data collection and spectral record production. when in real-time mode, the output data rate reflects the sr0 setting. table 29 provides a list of srx settings available in the avg_cnt register (see table 28), along with the resulting sample rates, fft bin widths, bandwidth, and estimated total noise. note that each srx setting also has associated range settings in the rec_ctrl2 register (see table 30) and the fft averaging settings that are shown in the fft_avg1 and fft_avg2 registers (see table 34 and table 35, respectively). table 28. avg_cnt page 1-6, low byte address = 0x32, read/write bits description (default = 0x9630) [15:12] sample rate option 3, binary (0 to 10), sr3 option sample rate = 20,000 2 avg_cnt[15:12] [11:8] sample rate option 2, binary (0 to 10), sr2 option sample rate = 20,000 2 avg_cnt[11:8] [7:4] sample rate option 1, binary (0 to 10), sr1 option sample rate = 20,000 2 avg_cnt[7:4] [3:0] sample rate option 0, binary (0 to 10), sr0 option sample rate = 20,000 2 avg_cnt[3:0] table 29. sample rate settings and filter performance srx option sample rate, f s (sps) bin width (hz) bandwidth (hz) peak noise per bin (m g ) 0 20,000 39.1 10,000 5.18 1 10,000 19.5 5,000 3.66 2 5,000 9.8 2,500 2.59 3 2,500 4.9 1,250 1.83 4 1,250 2.4 625 1.29 5 625 1.2 313 0.91 6 313 0.6 156 0.65 7 156 0.3 78 0.46 8 78 0.2 39 0.32 9 39 0.1 20 0.23 10 20 0.0 10 0.16 figure 16. signal flow diagram, rec_ctrl1[1:0] = 00 or 01, fft analysis modes
adis16000/adis16229 preliminary technical data rev. pra | page 18 of 37 figure 17. spectral record production, with all srx settings enabled
preliminary technical data adis16000/adis16229 rev. pra | page 19 of 37 dynamic range/sensitivity the range of the adis16229 accelerometers depends on the frequency of the vibration. the accelerometers have a self- resonant frequency of 5.5 khz, and the signal conditioning circuit applies a single-pole, low-pass filter (2.5 khz) to the response. the self-resonant behavior of the accelerometer influences the relationship between vibration frequency and dynamic range, as shown in figure 18, which displays the response to peak input amplitudes, assuming a sinusoidal vibration signature at each frequency. the accelerometer resonance and low-pass filter also influence the magnitude response, as shown in figure 19. 20 0 2 4 6 8 10 12 14 16 18 1000 2000 4000 5000 6000 peak magnitude ( g ) frequency (hz) 10069-116 2 g peak response 14 g peak response 16 g peak response 18 g peak response figure 18. peak magnitude vs. frequency 100 1000 5000 mean magnitude ( g ) frequency (hz) 10069-117 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 ?3 +3 figure 19. magnitude/frequency response (cal_enable[4] = 0) dynamic range settings rec_ctrl2 (see table 30) provides four range settings that are associated with each sample rate option, srx. the range options that are referenced in rec_ctrl2 reflect the maximum dynamic range, which occurs at the lower part of the frequency range and does not account for the decrease in range (see figure 18). for example, set rec_ctrl2[5:4] = 10 (din = 0x9c20) to set the peak acceleration (a max ) to 10 g on the sr2 sample rate option. these settings help optimize fft precision and sensitivity when monitoring lower magnitude vibrations. for each range setting in table 30, this stage scales the time domain data so that the maximum value equates to 2 15 lsbs for time domain data and 2 16 lsbs for frequency domain data. note that the maximum range for each setting is 1 lsb smaller than the listed maximum. for example, the maximum number of codes in the frequency domain analysis is 2 16 ? 1, or 65,535. for example, when using a range setting of 1 g in one of the fft modes, the maximum measurement is equal to 1 g times 2 16 ? 1, divided by 2 16 . see table 31 for the resolution associated with each setting and figure 16 for the location of this operation in the signal flow diagram. the real-time mode automatically uses the 20 g range setting. table 30. rec_ctrl2 page 1-6, low byte address = 0x1c, read/write bits description (default = 0x00ff) [15:8] not used (dont care) [7:6] measurement range, sr3 00 = 1 g , 01 = 5 g , 10 = 10 g , 11 = 20 g [5:4] measurement range, sr2 00 = 1 g , 01 = 5 g , 10 = 10 g , 11 = 20 g [3:2] measurement range, sr1 00 = 1 g , 01 = 5 g , 10 = 10 g , 11 = 20 g [1:0] measurement range, sr0 00 = 1 g , 01 = 5 g , 10 = 10 g , 11 = 20 g table 31. range settings and lsb weights range setting ( g ) (rec_ctrl2[5:4]) time mode (m g /lsb) fft mode (m g /lsb) 0 to 1 0.0305 0.0153 0 to 5 0.1526 0.0763 0 to 10 0.3052 0.1526 0 to 20 0.6104 0.3052
adis16000/adis16229 preliminary technical data rev. pra | page 20 of 37 scale adjustment the x_sens registers (see table 32 and table 33) provide a fine-scale adjustment function for each axis. the following equation describes how to use measured and ideal values to calculate the scale factor for each register in lsbs: scfx = ? ? ? ? ? ? ? 1 xm xi a a 2 18 where: xi a is the ideal x-axis value. xm a is the actual x-axis measurement. these registers contain correction factors, which come from the factory calibration process. the calibration process records accelerometer output in four different orientations and computes the correction factors for each register. these registers also provide write access for in-system adjust- ment. gravity provides a common stimulus for this type of correction process. use both +1 g and ?1 g orientations to reduce the effect of offset on this measurement. in this case, the ideal measurement is 2 g , and the measured value is the difference of the accelerometer measurements at +1 g and ?1 g orientations. the factory-programmed values are stored in flash memory and are restored by setting glob_cmd[3] = 1 (din = 0xb604) (see table 74). table 32. x_sens pages 1-6, low byte address = 0x16, read/write bits description (default = n/a) [15:0] x-axis scale correction factor (scfx), twos complement table 33. y_sens pages 1-6, low byte address = 0x18, read/write bits description (default = n/a) [15:0] y-axis scale correction factor (scfy), twos complement pre-fft windowing rec_ctrl1[13:12] provide three options for pre-fft windowing of time data. for example, set rec_ctrl1[13:12] = 01 to use the hanning window, which offers the best amplitude resolution of the peaks between frequency bins and minimal broadening of peak amplitudes. the rectangular and flat top windows are also available because they are common windowing options for vibration monitoring. the flat top window provides accurate amplitude resolution with a trade-off of broadening the peak amplitudes.
preliminary technical data adis16000/adis16229 rev. pra | page 21 of 37 fft the fft process converts each 512-sample time record into a 256-point spectral record that provides magnitude vs. frequency data. fft averaging the fft averaging function combines multiple fft records to reduce the variation of the fft noise floor, which enables detection of lower vibration levels. each srx option in the rec_ctrl1 register has its own fft average control, which establishes the number of fft records to average into the final fft record. to enable this function, write the number of averages for each srx option that is enabled in the rec_ctrl1 register to the fft_avgx registers. for example, set fft_avg2[8:0] = 0x4a (din = 0x904a) to set the number of fft averages to 16 for the sr2 sample rate option and 1024 for the sr3 sample rate option. table 34. fft_avg1 page 0, low byte address = 0x0e, read/write bits description (default = 0x0108) [15:8] fft averages for a single record, sr1 sample rate, n f in figure 16; range = 1 to 255, binary [7:0] fft averages for a single record, sr0 sample rate, n f in figure 16; range = 1 to 255, binary table 35. fft_avg2 page 0, low byte address = 0x10, read/write bits description (default = 0x0101) [15:8] fft averages for a single record, sr3 sample rate, n f in figure 16; range = 1 to 255, binary [7:0] fft averages for a single record, sr2 sample rate, n f in figure 16; range = 1 to 255, binary recording times when using automatic fft mode, the automatic recording period (rec_prd) must be greater than the total recording time. use the following equations to calculate the recording time: manual time mode t r = t s + t pt + t st + t ast fft modes t r = n f ( t s + t pt + t fft ) + t st + t ast table 36 provides a list of the processing times and settings that are used in these equations. table 36. typical processing times function time (ms) sample time, t s 1 f s , per avg_cnt processing time, t pt 18.7 fft time, t fft 32.7 number of fft averages, n f per fft_avg1, fft_avg2 storage time, t st 120.0 alarm scan time, t ast 2.21 the storage time (t st ) applies only when a storage method is selected in rec_ctrl1[3:2] (see table 27 for more details about the record storage settings). the alarm scan time (t ast ) applies only when the alarms are enabled in alm_ctrl[4:0] (see table 41 for more information). understanding the recording time helps predict when data is available, for systems that cannot use do1 to monitor the status of these operations. note that when using automatic fft mode, the automatic recording period (rec_prd) must be greater than the total recording time. data records after the adis16229 finishes processing fft data, it stores the data into the data buffer, where it is available for external access using the spi and x_buf registers (see table 59 and table 60). rec_ctrl1[3:2] (see table 27) provides programmable conditions for writing buffer data into the fft records, which are in nonvolatile flash memory locations. set rec_ctrl1[3:2] = 01 to store data buffer data into the flash memory records only when an alarm condition is met. set rec_ctrl1[3:2] = 10 to store every set of fft data into the flash memory locations. the flash memory record provides space for a total of 14 records. each record stored in flash memory contains a header and frequency domain (fft) data from all axes (x, and y). when all 14 records are full, new records do not load into the flash memory. the rec_cntr register (see table 37) provides a running count for the number of records that are stored. set glob_cmd[8] = 1 (din = 0xbf01) to clear all of the records in flash memory. table 37. rec_cntr page 0, low byte address = 0x50), read only bits description (default = 0x0000) [15:5] not used [4:0] total number of records taken; range = 0 to 14, binary when used in conjunction with automatic trigger mode and record storage, fft analysis for each sample rate option requires no addi- tional inputs. depending on the number of fft averages, the time between each sample rate selection may be quite large. note that selecting multiple sample rates reduces the number of records available for each sample rate setting, as shown in table 38. table 38. available records per sample rate selected number of sample rates selected available records 1 14 2 7 3 4 4 3 fft record flash endurance the rec_flsh_cnt register (see table 39) increments when all 14 records contain fft data.
adis16000/adis16229 preliminary technical data rev. pra | page 22 of 37 table 39. rec_flsh_cnt page 1-6, low byte address = 0x4a, read only bits description [15:0] flash write cycle count; record data only, binary
preliminary technical data adis16000/adis16229 rev. pra | page 23 of 37 sensor node spectral alarms the alarm function offers six spectral bands for alarm detection. each spectral band has high and low frequency definitions, along with two different trigger thresholds (alarm 1 and alarm 2) for each accelerometer axis. table 40 provides a summary of each register used to configure the alarm function. table 40. alarm function register summary register address description alm_f_low 0x20 alarm frequency band, lower limit alm_f_high 0x22 alarm frequency band, upper limit alm_x_mag1 0x24 x-axis alarm trigger level 1 (warning) alm_y_mag1 0x26 y-axis alarm trigger level 1 (warning) alm_x_mag2 0x2a x-axis alarm trigger level 2 (fault) alm_y_mag2 0x2c y-axis alarm trigger level 2 (fault) alm_pntr 0x2c alarm pointer alm_s_mag 0x2e system alarm trigger level alm_ctrl 0x30 alarm configuration diag_stat 0x34 alarm status alm_x_stat 0x38 x-axis alarm status alm_y_stat 0x3a y-axis alarm status alm_x_peak 0x3c x-axis alarm peak alm_y_peak 0x3e y-axis alarm peak alm_x_freq 0x44 x-axis alarm frequency of peak alarm alm_y_freq 0x46 y-axis alarm frequency of peak alarm the alm_ctrl register (see table 41) provides control bits that enable the spectral alarms of each axis, configures the system alarm, sets the record delay for the spectral alarms, and configures the clearing function for the diag_stat error flags (see table 84). table 41. alm_ctrl page 1-6, low byte address = 0x30, read/write bits description (default = 0x0000) [15:12] not used. [11:8] response delay; range = 0 to 15. represents the number of spectral records for each spectral alarm before a spectral alarm flag is set high. 7 latch diag_stat error flags. requires a clear status command (glob_cmd[4]) to reset the flags to 0. 1 = enabled, 0 = disabled. 6 enable do1 as an alarm 1 output indicator and enable do2 as an alarm 2 output indicator. 1 = enabled. 5 system alarm comparison polarity. 1 = trigger when less than alm_s_mag[11:0]. 0 = trigger when greater than alm_s_mag[11:0]. 4 system alarm. 1 = temperature, 0 = power supply. 3 alarm s enable (alm_s_mag). 1 = enabled, 0 = disabled. 2 not used 1 alarm y enable (alm_y_mag). 1 = enabled, 0 = disabled. 0 alarm x enable (alm_x_mag). 1 = enabled, 0 = disabled. alarm definition the alarm function provides six programmable spectral bands, as shown in figure 20. each spectral alarm band has lower and upper frequency definitions for all of the sample rate options (srx). it also has two independent trigger level settings, which are useful for systems that value warning and fault condition indicators. magnitude frequency 1 2 3 4 5 6 alm_f_high alm_f_low alm_x_mag1 alm_x_mag2 10069-020 figure 20. spectral band alarm setting example, alm_pntr = 0x03 select the spectral band for configuration by writing its number (1 to 6) to alm_pntr[2:0] (see table 42). then select the sample rate option using alm_pntr[9:8]. this number represents a binary number, which corresponds to the x in the srx sample rates option associated with rec_ctrl1[11:8] (see ). for example, set alm_pntr[7:0] = 0x05 (din = 0xac05) to select alarm spectral band 5, and set alm_pntr[15:8] = 0x02 (din = 0xb102) to select the sr2 sample rate option. table 42. alm_pntr page 1-6, low byte address = 0x2c, read/write bits description (default = 0x0000) [15:10] not used [9:8] sample rate option; range = 0 to 3 for sr0 to sr3 [7:3] not used [2:0] spectral band number; range = 1 to 6 alarm band frequency definitions after the spectral band and sample rate settings are set, program the lower and upper frequency boundaries by writing their bin numbers to the alm_f_low register (see table 43) and alm_f_high register (see table 44). use the bin width definitions listed in table 29 to convert a frequency into a bin number for this definition. calculate the bin number by dividing the frequency by the bin width that is associated with the sample rate setting. for example, if the sample rate is 5000 hz and the lower band frequency is 400 hz, divide that number by the bin width of 10 hz to arrive at the 40 th bin as the lower band setting. then set alm_f_low[7:0] = 0x28 (din = 0xa028) to establish 400 hz as the lower frequency for the 5000 sps sample rate setting. table 43. alm_f_low page 1-6, low byte address = 0x20, read/write bits description (default = 0x0000)
adis16000/adis16229 preliminary technical data rev. pra | page 24 of 37 [15:8] not used [7:0] lower frequency, bin number; range = 0 to 255 table 44. alm_f_high page 1-6, low byte address = 0x22, read/write bits description (default = 0x0000) [15:8] not used [7:0] upper frequency, bin number; range = 0 to 255 alarm trigger settings the alm_x_mag1 and alm_x_mag2 registers (see table 45 to table 48) provide two independent trigger settings for both axes of acceleration data. they use the data format established by the range settings in the rec_ctrl2 register (see table 30) and recording mode in rec_ctrl1[1:0] (see table 27). for example, when using the 0 g to 1 g mode for fft analysis, 32,768 lsb is the closest setting to 500 m g . therefore, set alm_y_mag2 = 0x8000 (din = 0xab80, 0xaa00) to set the critical alarm to 500 m g , when using the 0 g to 1 g range option in rec_ctrl2 for fft records. see table 30 and table 31 for more information about formatting each trigger level. note that trigger settings that are associated with alarm 2 should be greater than the trigger settings for alarm 1. in other words, the alarm magnitude settings should meet the following criteria: alm_x_mag2 > alm_x_mag1 alm_y_mag2 > alm_y_mag1 table 45. alm_x_mag1 page 1-6, low byte address = 0x24, read/write bits description (default = 0x0000) [15:0] x-axis alarm trigger level 1, 16-bit unsigned (see table 30 and table 31 for the scale factor) table 46. alm_y_mag1 page 1-6, low byte address = 0x26, read/write bits description (default = 0x0000) [15:0] y-axis alarm trigger level 1, 16-bit unsigned (see table 30 and table 31 for the scale factor) table 47. alm_x_mag2 page 1-6, low byte address = 0x2a, read/write bits description (default = 0x0000) [15:0] x-axis alarm trigger level 2, 16-bit unsigned (see table 30 and table 31 for the scale factor) table 48. alm_y_mag2 page 1-6, low byte address = 0x2c, read/write bits description (default = 0x0000) [15:0] y-axis alarm trigger level 2, 16-bit unsigned (see table 30 and table 31 for the scale factor) table 49. alm_s_mag page 1-6, low byte address = 0x2e, read/write bits description (default = 0x0000) [15:0] system alarm trigger level, data format matches target from alm_ctrl[4] enable alarm settings before configuring the spectral alarm registers, clear their current contents by setting glob_cmd[9] = 1 (din = 0xb702). after completing the spectral alarm band definitions, save the settings by setting glob_cmd[12] = 1 (din = 0xb710). the device ignores the save command if any of these locations has already been written to. alarm indicator signals gpo_ctrl[5:0] (see table 83) and alm_ctrl[6] (see table 41) provide controls for establishing do1 and do2 as dedicated alarm output indicator signals. use gpo_ctrl[5:0] to select the alarm function for do1 and/or do2; then set alm_ctrl[6] = 1 to enable do1 to serve as an alarm 1 indi-cator and do2 as an alarm 2 indicator. this setting establishes do1 to indicate alarm 1 (warning) conditions and do2 to indicate alarm 2 (critical) conditions. alarm flags and conditions the fft header (see table 69) contains both generic alarm flags (diag_stat[13:8]; seetable 84) and spectral band-specific alarm flags (alm_x_stat; see table 50, table 51) . the f f t header also contains magnitude (alm_x_peak; see table 52, table 53) and frequency information (alm_x_freq; see table 54, table 55) associated with the highest magnitude of vibration content in the record.
preliminary technical data adis16000/adis16229 rev. pra | page 25 of 37 alarm status the alm_x_stat registers (see table 50, table 51) provide alarm bits for each spectral band on the current sample rate option. table 50. alm_x_stat low byte address = 0x38, read only bits description (default = 0x0000) 15 alarm 2 on band 6; 1 = alarm set, 0 = no alarm 14 alarm 1 on band 6; 1 = alarm set, 0 = no alarm 13 alarm 2 on band 5; 1 = alarm set, 0 = no alarm 12 alarm 1 on band 5; 1 = alarm set, 0 = no alarm 11 alarm 2 on band 4; 1 = alarm set, 0 = no alarm 10 alarm 1 on band 4; 1 = alarm set, 0 = no alarm 9 alarm 2 on band 3; 1 = alarm set, 0 = no alarm 8 alarm 1 on band 3; 1 = alarm set, 0 = no alarm 7 alarm 2 on band 2; 1 = alarm set, 0 = no alarm 6 alarm 1 on band 2; 1 = alarm set, 0 = no alarm 5 alarm 2 on band 1; 1 = alarm set, 0 = no alarm 4 alarm 1 on band 1; 1 = alarm set, 0 = no alarm 3 not used [2:0] most critical alarm condition, spectral band; range = 1 to 6 table 51. alm_y_stat low byte address = 0x3c, read only bits description (default = 0x0000) 15 alarm 2 on band 6; 1 = alarm set, 0 = no alarm 14 alarm 1 on band 6; 1 = alarm set, 0 = no alarm 13 alarm 2 on band 5; 1 = alarm set, 0 = no alarm 12 alarm 1 on band 5; 1 = alarm set, 0 = no alarm 11 alarm 2 on band 4; 1 = alarm set, 0 = no alarm 10 alarm 1 on band 4; 1 = alarm set, 0 = no alarm 9 alarm 2 on band 3; 1 = alarm set, 0 = no alarm 8 alarm 1 on band 3; 1 = alarm set, 0 = no alarm 7 alarm 2 on band 2; 1 = alarm set, 0 = no alarm 6 alarm 1 on band 2; 1 = alarm set, 0 = no alarm 5 alarm 2 on band 1; 1 = alarm set, 0 = no alarm 4 alarm 1 on band 1; 1 = alarm set, 0 = no alarm 3 not used [2:0] most critical alarm condition, spectral band; range = 1 to 6 worst-case condition monitoring the alm_x_peak registers (see table 52, table 53) contain the peak magnitude for the worst-case alarm condition in each axis. the alm_x_freq registers (see table 54, table 55) contain the frequency bin number for the worst-case alarm condition. table 52. alm_x_peak page 1-6, low byte address = 0x3c, read only bits description (default = 0x0000) [15:0] alarm peak, x-axis, accelerometer data format table 53. alm_y_peak page 1-6, low byte address = 0x3e, read only bits description (default = 0x0000) [15:0] alarm peak, y-axis, accelerometer data format table 54. alm_x_freq page 1-6, low byte address = 0x44, read only bits description (default = 0x0000) [15:8] not used [7:0] alarm frequency for x-axis peak alarm level, fft bin number; range = 0 to 255 table 55. alm_y_freq page 1-6, low byte address = 0x46, read only bits description (default = 0x0000) [15:8] not used [7:0] alarm frequency for y-axis peak alarm level, fft bin number; range = 0 to 255
adis16000/adis16229 preliminary technical data rev. pra | page 26 of 37 reading output data after the adis16229 updates the adis16000 with its data, it is available in the data buffer and fft records (if selected). in manual time capture mode, the record for each axis contains 512 samples. in manual and automatic fft mode, each record contains the 256-point fft result for each accelerometer axis. table 56 provides a summary of registers that provide access to processed sensor data. table 56. output data registers register address description temp_out 0x0a internal temperature supply_out 0x0c internal power supply buf_pntr 0x12 data buffer index pointer rec_pntr 0x14 fft record index pointer x_buf 0x06 x-axis accelerometer buffer y_buf 0x08 y- axis accelerometer buffer glob_cmd 0x36 fft record retrieve command time_stamp_l 0x40 time stamp, lower word time_stamp_h 0x42 time stamp, upper word rec_info1 0x4c fft record header information rec_info2 0x4e fft record header information reading data from the data buffer after completing a spectral record and updating each data buffer, the adis16000 loads the first data sample from each data buffer into the x_buf registers (see table 59 and table 60) and sets the buffer index pointer in the buf_pntr register (see table 57) to 0x0000. the index pointer determines which data samples load into the x_buf registers. for example, writing 0x009f to the buf_pntr register (din = 0x9300, din = 0x929f) causes the 160th sample in each data buffer location to load into the x_buf registers. the index pointer increments with every x_buf read command, which causes the next set of capture data to load into each capture buffer register automatically. this enables an efficient method for reading all 256 samples in a record, using sequential read commands, without having to manipulate the buf_pntr register. figure 21. data buffer structure and operation table 57. buf_pntr page 1-6, low byte address =10, read/write bits description (default = 0x0000) [15:9] not used [8:0] data bits; range = 0 to 255 (fft), 0 to 511 (time) accessing fft record data the fft records can be stored in flash memory. the rec_pntr register (see table 58) and glob_cmd[13] (see table 74) provide access to the fft records, as shown in figure 22. for example, set rec_pntr[7:0] = 0x0a (din = 0x940a) and glob_cmd[13] = 1 (din = 0xb720) to load fft record 10 in the fft buffer for spi/register access. table 58. rec_pntr page 1-6, low byte address = 0x14, read/write bits description (default = 0x0000) [15:4] not used [3:0] data bits figure 22. fft record access
preliminary technical data adis16000/adis16229 rev. pra | page 27 of 37 data format table 59 and table 60 list the bit assignments for the x_buf registers. the acceleration data format depends on the range scale setting in rec_ctrl2 (see table 30) and the recording mode settings in rec_ctrl1 (see table 27). table 61 provides some data formatting examples for the fft mode, and table 62 offers some data formatting examples for the16-bit, twos complement format used in manual time mode. table 59. x_buf low byte address = 0x06, read only bits description (default = 0x8000) [15:0] x-acceleration data buffer register. see table 31 for scale sensitivity. format = twos complement (time), binary (fft). table 60. y_buf low byte address = 0x08, read only bits description (default = 0x8000) [15:0] y-acceleration data buffer register. see table 31 for scale sensitivity. format = twos complement (time), binary (fft). table 61. fft mode, 5 g g acceleration (mg) lsb hex binary 4,999.9237 65,535 0xffff 1111 1111 1111 1111 100 5 65,536 100 0x0064 0000 0000 0110 0100 2 5 65,536 2 0x0002 0000 0000 0000 0010 1 5 65,536 1 0x0001 0000 0000 0000 0001 0 0 0x0000 0000 0000 0000 0000 table 62. manual time mode, 5 g g acceleration (m g ) lsb hex binary +4999.847 +32,767 0x7fff 1111 1111 1111 1111 ~1000 +6,554 0x199a 0001 0001 10011010 +2 5 32,768 +2 0x0002 0000 0000 0000 0010 +1 5 32,768 +1 0x0001 0000 0000 0000 0001 0 0 0x0000 0000 0000 0000 0000 ?1 5 32,768 ?1 0xffff 1111 1111 1111 1111 ?2 5 32,768 ?2 0xfffe 1111 1111 1111 1110 ~?1000 ?6554 0xe666 1110 0110 0110 0110 ?5000 ?32,768 0x8000 1000 0000 0000 0000 real-time data collection when using real-time mode, select the output channel by reading the associated x_buf register. for example, set din = 0x1600 to select the y-axis sensor for sampling. after selecting the channel, use the data-ready signal to trigger subsequent data reading of the y_buf register. in this mode, use the time domain data formatting for a range setting of 20 g , as shown in table 31. power supply/temperature at the end of each spectral record, the adis16229 also measures power supply and internal temperature. it accumulates a 5.12 ms record of power supply measurements at a sample rate of 50 khz and takes 64 samples of internal temperature data over a period of 1.7 ms. the average of the power supply and internal tempera-ture loads into the supply_out register (see table 64 and table 65) and the temp_out registers (see table 66 and table 67), respectively. when using real-time mode, these registers update only when this mode starts. table 63. supply_out page 0, low byte address = 0x0c, read only bits description (default = 0x8000) [15:12] not used [11:0] power supply, binary, 3.3 v = 0xa8f, 1.22 mv/lsb table 64. supply_out page 1- 6, low byte address = 0x0a, read only bits description (default = 0x8000) [15:12] not used [11:0] power supply, binary, 3.3 v = 0xa8f, 1.22 mv/lsb table 65. power supply data format examples supply level (v) lsb hex binary 3.6 2949 0xb85 1011 1000 0101 3.3 + 0.0012207 2704 0xa90 1010 1001 0000 3.3 2703 0xa8f 1010 1000 1111 3.3 ? 0.0012207 2702 0xa8e 1010 1000 1110 3.15 2580 0xa14 1010 0001 0100 table 66. temp_out page 0, low byte address = 0x0e, read only bits description (default = 0x8000) [15:12] not used [11:0] temperature data, offset binary, 1278 lsb = +25c, ?0.47c/lsb table 67. temp_out page 1-6, low byte address = 0x0c8, read only bits description (default = 0x8000) [15:12] not used [11:0] temperature data, offset binary, 1278 lsb = +25c,
adis16000/adis16229 preliminary technical data rev. pra | page 28 of 37 ?0.47c/lsb table 68. internal temperature data format examples temperature (c) lsb hex binary 125 1065 0x429 0100 0010 1001 25 + 0.47 1277 0x4fd 0100 1111 1101 25 1278 0x4fe 0100 1111 1110 25 ? 0.47 1279 0x4ff 0100 1111 1111 0 1331 0x533 0101 0011 0011 ?40 1416 0x588 0101 1000 1000
preliminary technical data adis16000/adis16229 rev. pra | page 29 of 37 fft event header each fft record has an fft header that contains information that fills all of the registers listed in table 69. the information in these registers contains recording time, record configuration settings, status/error flags, and several alarm outputs. the registers listed in table 69 update with every record event and also update with record-specific information when using glob_cmd[13] (see table 74) to retrieve a data set from the fft record in flash memory. table 69. fft header register information register address description diag_stat 0x34 alarm status alm_x_stat 0x38 x-axis alarm status alm_y_stat 0x3a y-axis alarm status alm_x_peak 0x3c x-axis alarm peak alm_y_peak 0x3e y-axis alarm peak time_stmp_l 0x40 time stamp, lower word time_stmp_h 0x42 time stamp, upper word alm_x_freq 0x44 x-axis alarm frequency of peak alarm alm_y_freq 0x46 y-axis alarm frequency of peak alarm rec_info1 0x4c fft record header information rec_info2 0x4e fft record header information the rec_info1 register (see table 70) and the rec_info2 register (see table 71) capture the settings associated with the current fft record. table 70. rec_info1 page 1-6, low byte address = 0x4e), read only bits description [15:14] sample rate option 00 = sr0, 01 = sr1, 10 = sr2, 11 = sr3 [13:12] window setting 00 = rectangular, 01 = hanning, 10 = flat top, 11 = n/a [11:10] signal range 00 = 1 g , 01 = 5 g , 10 = 10 g , 11 = 20 g [9:8] not used (dont care) [7:0] fft averages; range = 1 to 255 table 71. rec_info2 page 1-6, low byte address = 0x4e, read only bits description [15:4] not used (dont care) [3:0] avg_cnt setting the time_stmp_x registers (see table 72 and table 73) provide a relative time stamp that identifies the time for the current fft record. table 72. time_stmp_l page 1-6, low byte address = 0x40, read only bits description (default = 0x0000) [15:0] record time stamp, low integer, binary, seconds table 73. time_stmp_h page 1-6, low byte address = 0x42, read only bits description (default = 0x0000) [15:0] record time stamp, high integer, binary, seconds
adis16000/adis16229 preliminary technical data rev. pra | page 30 of 37 system tools global commands the glob_cmd register (see table 74) provides an array of single-write commands for convenience. setting the assigned bit to 1 activates each function. when the function completes, the bit restores itself to 0. for example, clear the capture buffers by setting glob_cmd[8] = 1 (din = 0xb701). all of the commands in the glob_cmd register require that the power supply be within normal limits for the execution times listed in table 74. table 74. glob_cmd page 1-6, low byte address = 0x36, write only bits description execution time 15 clear autonull correction 35 s 14 retrieve spectral alarm band infor- mation from the alm_pntr setting 40 s 13 retrieve record data from flash memory 1.9 ms 12 save spectral alarm band registers to sram 461 s 11 record start/stop n/a 10 set buf_pntr = 0x0000 36 s 9 clear spectral alarm band registers from flash memory 25.8 ms 8 clear records 25.9 ms 7 software reset 52 ms 6 save registers to flash memory 29.3 ms 5 flash test, compare sum of flash memory with factory value 5 ms 4 clear diag_stat register 36 s 3 restore factory register settings and clear the capture buffers 84 ms 2 self-test, result in diag_stat[5] 32.9 ms 1 power-down n/a 0 autonull 822 ms device identification table 75. lot_id1 page = 0, low byte address = 0x1a, read only bits description [15:0] lot identification code table 76. lot_id1 page = 1-6, low byte address = 0x68, read only bits description [15:0] lot identification code table 77. lot_id2 page 0, low byte address = 0x1c, read only bits description [15:0] lot identification code table 78. lot_id2 page 1-6, low byte address = 0x6a, read only bits description [15:0] lot identification code table 79. prod_id page 0, low byte address = 0x16), read only bits description (default = 0x3e80 [15:0] 0x3e80 = 16,000 table 80. prod_id page 0, low byte address = 0x48), read only bits description (default = 0x3e80 [15:0] 0x3f65 = 16,229 table 81. serial_num (base address = 0x58), read only bits description [15:0] serial number, lot specific table 82 shows a blank register that is available for writing user- specific identification. table 82. user_id (base address = 0x5c), read/write bits description (default = 0x000) [15:0] user-written identification table 83. gpo_ctrl page 0, low byte address = 0x2a, read/write bits description (default = 0x) [15:6] not used [5:4] do2 function selection 00 = general purpose 01 = alarm indicator 10 = busy indicator/data-r eady (real-time mode) 11 = not used [3:2] do1 function selection 00 = general purpose 01 = alarm indicator 10 = busy indicator/data-r eady (real-time mode) 11 = not used 1 do2 polarity 1 = active high
preliminary technical data adis16000/adis16229 rev. pra | page 31 of 37 0 = active low 0 do1 polarity 1 = active high 0 = active low status/error flags critical system error flags are in the diag_stat register for each adis16229. these flags indicate various error or alarm conditions that may influence system performance. multiple flags in these registers can be high at one time and the flags will persist (go high again, after clearing) when the error conditions continue to exist. the flags in bits 0 through 6 will remain in a latch condition, until clearing the problem or clearing (using use glob_cmd[4]). the alarm flags (upper byte) will latch if alm_ctrl[7] = 1 (see table 41) table 84. diag_stat page 1-6, low byte address = 0x34, read/write bits description (default = 0x) 15 not used 14 system alarm (1 = error condition exists, 0 = no error) 13 not used 12 sensor node 6 (1 = alarm condition, 0 = no alarm) 11 sensor node 5 (1 = alarm condition, 0 = no alarm) 10 sensor node 4 (1 = alarm condition, 0 = no alarm) 9 sensor node 3 (1 = alarm condition, 0 = no alarm) 8 sensor node 2 (1 = alarm condition, 0 = no alarm) 7 sensor node 1 (1 = alarm condition, 0 = no alarm) 6 flash memory failure, from glob_cmd[5] test [5:4] not used 3 spi communication failure (sclks even multiple of 16) 2 flash update failure 1 power supply > 3.625 v 0 power supply < 3.125 v self-test set glob_cmd[2] = 1 (din = 0xbe02) (see table 74) to run an automatic self-test routine, which reports a pass/fail result to diag_stat[5] (see table 84). flash memory management set glob_cmd[5] = 1 (din = 0xb620) to run an internal checksum test on the flash memory, which reports a pass/fail result to diag_stat[6]. the flash_cnt register (see table 85) provides a running count of flash memory write cycles. this is a tool for managing the endurance of the flash memory. figure 23 quantifies the relationship between data retention and junction temperature. table 85. flash_cnt page 1-6, low byte address = 0x04, read only bits description [15:0] binary counter for writing to flash memory 600 450 300 150 0 30 40 retention (years) junction temperature (c) 55 70 85 100 125 135 150 10069-015 figure 23. flash?/ee memory data retention
adis16000/adis16229 preliminary technical data rev. pra | page 32 of 37 applications information interface board the adis16com1/pcbz accessory provides a direct attachment method for connecting the adis16000cmlz directly to the eval-adis evaluation system. mating connector tbd figure 24. pcb assembly view and dimensions figure 25. mating connector detail figure 26. electrical schematic
preliminary technical data adis16000/adis16229 rev. pra | page 33 of 37 outline dimensions
adis16000/adis16229 preliminary technical data rev. pra | page 34 of 37 figure 27. 14-lead module with connector interface (ml-14-2)) dimensions shown in millimeters
preliminary technical data adis16000/adis16229 rev. pra | page 35 of 37
adis16000/adis16229 preliminary technical data rev. pra | page 36 of 37 figure 28. remote sensor with sma antenna interface (ml-1-1) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ADIS16000AMLZ ?40c to +85c 14-lead module with connector interface and sma antenna interface ml-14-2 adis16com1/pcbz evaluation board adis16229amlz ?40c to +85c sensor module with sma antenna interface ml-1-1 1 z = rohs compliant part.
data sheet adis16000/adis16229 rev. pra | page 37 of 37 notes ?2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. pr11483-0-5/13(pra)

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